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Protection for the lower wires cannot use low-k dielectrics, but must use relatively higher capacitance (C) oxides.
However, the increased RC delay in the lower interconnects is more than offset by the orders-of-magnitude reduction in interconnect lengths due to vertical stacking.
In addition, this approach will work well for integrating new channel materials such as III-V’s and germanium, and any materials that can be deposited at relatively low temperatures such as the active layers in gas-sensors or resistive-memory cells.” Non-Equilibrium Thermal Processing Though the use of an oxide barrier between the active device layers provides significant thermal protection to the bottom layer of devices during top-layer fabrication, the thermal processes of the latter cannot be run at equilibrium.
“One way of controlling the thermal budget is to use what we sometimes call the crème brûlée approach to only heat the very top surface while keeping the inside cool,” explained Vinet.
Leti has already shown proof-of-concept for processes that integrate new IC functionalities into future M3D stacks: 1) CMOS: CMOS, 2) PMOS: NMOS, 3) III-V: Ge, and 4) MEMS/NEMS: CMOS.
Thomas Ernst, senior scientist, Electron Nanodevice Architectures, Leti, commented to , “Any application that will need a ‘pixelated’ device architecture would likely use M3D.
“Laser non-equilibrium heating is enabling technology for 3D devices,” affirmed Steve Moffatt, chief technology officer, Front End Products, Applied Materials.
“The idea is to heat the top layer and not the layers below.
Since neither aluminum nor copper interconnects can withstand this temperature range, the interconnects for the bottom layer of transistors need to be tungsten wires with the highest melting point of any metal but somewhat worse electrical resistance (R).Leti’s approach to 3D stacking of transistors starts with a conventionally built and locally-interconnected bottom layer of transistors, which are then covered with a top layer of transistors built using relatively low-temperature processes branded as “Cool Cube.” Figure 1 shows a simplified cross-sectional schematic of a Cool Cube stack of transistors and interconnects.Cool Cube M3D does not transfer a layer of built devices as in the approach using TSV, but instead transfers just a nm-thin layer of homogenous semiconducting material for subsequent device processing.“Everyone knows that you want a nice crispy top surface with cool custard beneath.” Using a laser with a short wavelength prevents penetration into lower layers such that essentially all of the energy is absorbed in the surface layer in a manner that can be considered as adiabatic.Applied Materials has been a supplier-partner with Leti in developing M3D, and the company provided responses from executive technologists to queries from about the general industry trend to controlling short pulses of light for thermal processing.
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Laser non-equilibrium heating in this regime can be a critical process for building monolithic 3D structures for SOC and logic devices.” Of course, with ultra-shallow junctions (USJ) and atomic-scale gate-stacks already in use for CMOS transistors at the 22nm-node, non-equilibrium thermal processing has already been used in leading fabs.